This invention relates generally to semiconductor memories, and more particularly to semiconductor flash memories.
There are many different types of memories that can be fabricated using semiconductors. One type of memory is random-access memory (RAM), which is a volatile memory. The memory can be programmed and erased to hold information while power is being supplied. However, when power is not supplied, the memory loses its contents. Another type of memory is read-only memory (ROM), which is a non-volatile memory. The memory cannot be reprogrammed nor erased, but retains its contents even when power is not supplied to the memory.
Other kinds of memories include programmable read-only memories (PROM""s), erasable PROM""s (EPROM""s), and electrically erasable PROM""s (EEPROM""s, or E2PROM""s). These types of memory are like ROM""s in that they are non-volatile, retaining their content contents even when power is not supplied. However, unlike ROM""s, they are programmable. In the case of PROM""s, they are programmable once, whereas in the case of EPROM""s and EEPROM""s, they can be erased, such as by applying ultraviolet (UV) light for EPROM""s, and electrically for EEPROM""s, and then reprogrammed.
A special type of EEPROM is the memory. Whereas EEPROM""s must be erased one byte at a time, flash memories can be erased a section at a time, and thus much more quickly. Like other memories, a flash memory has a grid of columns and rows, with a memory cell at each intersection. FIG. 1 shows an example flesh memory cell 100. The flash memory cell includes n+ regions 102 and 104 within a channel substrate 105. The n+ region 102 functions as the source, whereas the n+ region 104 functions as the drain. There is a floating gate 108 and a control gate 106, each of which can be polysilicon, or poly for short. The flash memory cell 100 is a split-gate flash memory cell. The control gate 106 is connected to a word line.
During a read operation, a voltage is applied to the control gate 106. If the floating gate 108 has been programmed, the transistor formed by the source 102, the channel 105, and the drain 104 will not conduct. Conversely, if the floating gate 108 has not been programmed, then the transistor will conduct. The conducting state is output as a logic one, whereas the non-conducting state is output as a logic zero. To erase the programming of the floating gate 108, the channel 105 is placed into inversion to deplete the charge from the floating gate 108. Conversely, to write or program the floating gate 108, charge is placed onto the floating gate 108.
Often, once a flash memory has been programmed to a given state, it is desirable to protect one or more blocks of the memory, effectively transforming these parts of the flash memory into a ROM. For example, a flash memory may include data and a programming routine for changing the data. If the memory becomes corrupted due to power supply or other problems, the memory cannot be programmed, because the programming routine has also been corrupted. However, if the programming routine is write protected, so that it has been transformed into ROM, then even if the data is corrupted, the flash memory can be reprogrammed, since the programming routine remains intact.
FIG. 2 shows the overall process used to transform flash memory into ROM, as the method 200. First, the high-voltage device for the block(s) of the flash memory to be protected is disabled, or removed (202). These high-voltage devices are those that enable the contents of the flash memory to be erased. Thus, an external high-voltage source is required to erase the selected block(s) of the flash memory, which in practical application where such an external source is unavailable, effectively means that the block(s) cannot be erased. Second, at least part of the charge pump for these block(s) are also disabled (204). The charge pumps normally enable these block(s) of the flash memory to be programmed. Without operative charge pumps, the block(s) cannot be programmed.
Finally, a p+ layer is implanted in the pxe2x88x92 substrate of the flash memory cells of the block(s) to be disabled, to act as device-disable layers for these individual flash memory cells (206). The p+ implant is also referred to as a code implant. FIG. 3 shows the traditional approach for this implantation. A code implant mask 302 with a hole 304 is positioned over the polysilicon gates 106 (the gate 108 having been removed to disable the memory cell 300), and p+ particles are implanted into the pxe2x88x92 substrate 122, as indicated by the arrow 306. This results in the p+ implant layer 308 within the pxe2x88x92 substrate 122. The p+ layer 308 further serves to transform the flash memory cell 300 into a ROM cell.
The approach outlined in FIG. 3, however, only works for 0.5-micron semiconductor processes. Semiconductor processes are continually shrinking, so that semiconductor devices, like memories, can become smaller, faster, and have higher densities. For 0.35-micron processes in particular, the p+ layer implantation approach of FIG. 3 does not work. This is because for 0.35-micron process flash memories, one or both of the polysilicon gatesxe2x80x94that is one or both of the control gate and the floating gatexe2x80x94are thicker than in 0.5-micron process flash memories. The added thickness of the gates, while enabling the flash memories to function, inhibits implantation of p+ particles into the pxe2x88x92 substrate.
One solution that has been used with limited success is to implant the p+ particles at the edge of the code implant mask, at an angle, to fabricate the p+ layer. FIG. 4 shows this improved approach. Rather than implanting the p+ particles through the hole 304 of the code implant mask 302, as was accomplished in the approach of FIG. 3, implantation of the p+ particles is performed at an angle, to either or both sides of the mask 302, as indicated by the arrows 402 and 404. This forms the p+ layer 308 as before. In this way, the p+ implantation does not have to proceed through the polysilicon gates 106 and 108, which, because of their increased thickness, inhibit the implantation. The angles 406 and 408 of the implantations indicated by the lines 402 and 404, respectively, usually are less than forty-five degrees.
However, in some densely packed parts of some flash memories, or in some wholly densely packed flash memories, even this improved approach does not work. This is explained with reference to FIG. 5, which shows a flash memory section 500. The flash memory section 500 has flash memory cells 502, 504, and 506. Each cell has a source, a drain, and a substrate, as the memory cell 100 of FIG. 1 does, but which are not numbered for purposes of illustrative clarity. Each cell also has a transistor gate, where the flash memory cell 502 has the gate 508, the memory cell 504 has the gate 510, and the cell 506 has the gate 512.
A code implant mask 514 is again positioned over one of the memory cells, in this case the memory cell 504, to implant a p+ layer within the substrate of the memory cell 504. Because the gate 510 of the cell 504 are sufficiently thick, the p+ particles cannot be implanted through the gate 510 as before. However, the p+ particles also cannot be implanted at the edges of the mask 514, at an angle, as they could with the memory cell 400 of FIG. 4. This is because the memory cells 502, 504, and 506 are too close to one another, and in particular, their gates are too close to one another. For example, attempting to implant at the left edge of the mask 514 at an angle, as indicated by the arrow 516, is not possible, because the gate 508 of the cell 502 are in the way. Similarly, implanting at the right edge of the mask 516 at an angle, as indicated by the arrow 518, is not possible, because the gate 512 of the cell 506 are in the way.
It has been found that if the spacing of the gates of individual cells is not at least 0.9 micron, then angled mask-edge p+ layer implantation is not possible. This means that for flash memories having densely packed sections, or for densely packed flash memories more generally, such memories, or blocks of such memories, cannot be transformed into ROM""s, because p+ layer implantation is not possible. This limitation reduces the utility of newer flash memories, relegating their use only in situations where conversion of one or more blocks of such memories to ROM is not needed or desirable.
Therefore, there is a need to overcome these described disadvantages with transforming flash memories to ROM""s. In particular, there is a need for an improved process to help transform the flash memory cell to a ROM cell, to cut off the pxe2x88x92 substrate, as has traditionally been accomplished with p+ layer implantation. Such an improved process should be able to be performed even where the individual flash memory cells of a flash memory are close together, such as where the gates of the individual cells are less than 0.9 micron apart. For these and other reasons, there is a need for the present invention.
The invention relates to disabling flash memory cells to protect their contents, thus essentially transforming them into read-only memory (ROM) cells. A gate mask and an implant code mask are positioned over a given flash memory cell. A field oxide layer is then fabricated within a substrate layer of the cell through the masks as logically and""ed together. By such fabrication, the flash memory cell is at least partially disabled. The masks are preferably a gate mask and an implant code mask, as these masks typically are already existing and available for use.
The invention provides for advantages over the prior art. A flash memory cell is transformed to a ROM cell by cutting off the pxe2x88x92 substrate of the flash memory cell, but with the use of a field oxide layer instead of p+ layer implantation. This means that the disadvantages of using p+ layer implantation are avoided. Specifically, the flash memory disabling process of the invention can be performed even where the individual flash memory cells of a flash memory are close together, and even where the gates of the cells are thick. Thus, the disabling process of the invention can be used in 0.35-micron process flash memories, where the flash memory cells of such memories may be less than 0.9 micron apart.
Still other advantages, aspects, and embodiments of the invention will become apparent by reading the detailed description that follows, and by referencing the accompanying drawings.